View ADF4360-7BCPRL7_5624476.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated synthesizer and vco adf4360-7 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures output freq ue ncy range: 350 mhz to 18 00 m hz divid e -by- 2 o u tput 3.0 v to 3.6 v p o wer supply 1.8 v logic compatibility integer-n synt hesizer programmable dua l -modul us prescaler 8/9, 1 6 /17 programmable output power level 3-wire seri al in terface analo g and d i gital lo ck de tect hardware and software power-down mode applic a t io ns wireless han d s e ts (dect, gsm , pcs, dcs, wcdma) test eq uipmen t wireless lans catv equipment gener a l description the ad f4360-7 is a n in t e g r a t e d in teg e r - n sy n t h e sizer and v o l t a g e con t r o l l ed os cil l a t o r ( v co). th e ad f4 360-7 cen t er f r e q u e nc y i s s e t b y e x te r n a l i ndu c t or s . t h i s a l l o w s a f r e q u e nc y ra n g e o f betw een 350 mh z t o 1 800 mh z. i n addi tion, a di vide- b y -2 o p t i o n is a v a i lab l e , w h er eb y t h e us er r e cei v es a n rf o u t p u t o f between 175 mh z and 900 mh z. c o n t ro l of a l l t h e on - c h i p re g i st e r s i s t h rou g h a s i m p l e 3 - w i re in t e r f ace . the de v i ce o p er a t es wi t h a p o w e r s u p p l y ra n g in g f r o m 3.0 v to 3.6 v and can b e p o w e r e d do w n w h e n n o t i n us e. func ti on a l bl ock di a g r a m muxout cp v vco ref in clk data le av dd dv dd r set agnd dgnd cpgnd ce v tune c c c n l1 l2 rf out a rf out b vco core phase comparator mute divsel = 2 divsel = 1 n = (bp + a) load load charge pump output stage mu l t i pl exer integer register 13-bit b counter 14-bit r counter 24-bit function latch 24-bit data register 5-bit a counter prescaler p/p+1 multiplexer lock detect 2 a d f 4 360-7 04441-001 fi g u r e 1 .
adf4360-7 rev. a | page 2 of 28 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 transistor c ount ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 circuit description ......................................................................... 10 reference input section ............................................................. 10 prescaler (p/p + 1) ...................................................................... 10 a and b counters ....................................................................... 10 r counter .................................................................................... 10 pfd and charge pump .............................................................. 10 muxout and lock detect ...................................................... 11 input shift register ..................................................................... 11 vco .............................................................................................. 11 output stage ................................................................................ 12 latch structure ........................................................................... 13 power-up ..................................................................................... 17 control latch .............................................................................. 19 n counter latch ......................................................................... 20 r counter latch ......................................................................... 20 applications ..................................................................................... 21 frequency generator ................................................................. 21 choosing the correct inductance value ................................. 22 fixed frequency lo ................................................................... 22 interfacing ................................................................................... 23 pcb design guidelines for chip scale package ........................... 23 output matching ........................................................................ 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 11/04rev. 0 to rev. a. updated format..................................................................universal changes to general description .................................................... 1 changes to specifications ................................................................ 3 changes to the reference input section...................................... 10 changes to power-up section ...................................................... 17 added table 10 ............................................................................... 17 added figure 22.............................................................................. 17 updated outline dimensions ....................................................... 25 2/04revision 0: initial version.
adf4360-7 rev. a | page 3 of 28 specifications 1 av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. table 1. parameter b version unit conditions/comments ref in characteristics ref in input frequency 10/250 mhz min/max for f < 10 mhz, use a dc-coupled cmos-compatible square wave, slew rate > 21 v/s. ref in input sensitivity 0.7/av dd v p-p min/max ac-coupled. 0 to av dd v max cmos compatible. ref in input capacitance 5.0 pf max ref in input current 60 a max phase detector phase detector frequency 2 8 mhz max charge pump i cp sink/source 3 with r set = 4.7 k?. high value 2.5 ma typ low value 0.312 ma typ r set range 2.7/10 k? i cp three-state leakage current 0.2 na typ sink and source current matching 2 % typ 1.25 v v cp 2.5 v. i cp vs. v cp 1.5 % typ 1.25 v v cp 2.5 v. i cp vs. temperature 2 % typ v cp = 2.0 v. logic inputs v inh , input high voltage 1.5 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 3.0 pf max logic outputs v oh , output high voltage dv dd C 0.4 v min cmos output chosen. i oh , output high current 500 a max v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 3.0/3.6 v min/v max dv dd av dd v vco av dd ai dd 4 10 ma typ di dd 4 2.5 ma typ i vco 4 , 5 14.0 ma typ i core = 5 ma. i rfout 4 3.5 to 11.0 ma typ rf o utput stage is programmable. low power sleep mode 7 a typ specifications continued on next page.
adf4360-7 rev. a | page 4 of 28 parameter b version unit conditions/comments rf output characteristics 5 maximum vco output frequency 1800 mhz i core = 5 ma. depending on l. see the choosing the correct inductance value section. minimum vco output frequency 350 mhz vco output frequency 490/585 mhz min/max l1, l2 = 13 nh. see the choosing the correct inductance value section for other frequency values. vco frequency range 1.2 ratio f max /f min vco sensitivity 12 mhz/v typ l1, l2 = 13 nh. see the choosing the correct inductance value section for other sensitivity values. lock time 6 400 s typ to within 10 hz of final frequency. frequency pushing (open loop) 6 mhz/v typ frequency pulling (open loop) 15 khz typ into 2.00 vswr load. harmonic content (second) ?19 dbc typ harmonic content (third) ?9 dbc typ output power 5 , 7 ?14/?5 dbm typ programmable in 3 db steps. see table 7. output power variation 3 db typ for tuned loads, see output matching section. vco tuning range 1.25/2.5 v min/max noise characteristic 5 vco phase-noise performance 8 ?116 dbc/hz typ @ 100 kh z offset from carrier. ?138 dbc/hz typ @ 1 mhz offset from carrier. ?144 dbc/hz typ @ 3 mhz offset from carrier. ?148 dbc/hz typ @ 10 mhz offset from carrier. synthesizer phase-noise floor 9 ?172 dbc/hz typ @ 25 khz pfd frequency. ?163 dbc/hz typ @ 200 khz pfd frequency. ?147 dbc/hz typ @ 8 mhz pfd frequency. in-band phase noise 10 , 11 ?92 dbc/hz typ @ 1 khz offset from carrier. rms integrated phase error 12 0.3 degrees typ 100 hz to 100 khz. spurious signals due to pfd frequency 11, 13 ?70 dbc typ level of unlocked signal with mtld enabled ?44 dbm typ 1 operating temperature range is C40c to +85c. 2 guaranteed by design. sample tested to ensure compliance. 3 i cp is internally modified to maintain constant loop gain over the frequency range. 4 t a = 25c; av dd = dv dd = v vco = 3.3 v; p = 32. 5 unless otherwise stated, these characteristics are guaranteed for vco core po wer = 5 ma. l1, l2 = 13 nh, 470 ? resistors to gn d in parallel with l1, l2. 6 jumping from 490 mhz to 585 mhz. pfd frequency = 200 khz; loop bandwidth = 10 khz. 7 using 50 ? resistors to v vco , into a 50 ? load. for tuned loads, see the output m section. atching 8 the noise of the vco is meas ured in open-loop conditions. 9 the synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0 log n (where n is the n divider value). 10 the phase noise is measured with the eval-adf4360-xe b1 evaluation board and the hp 8562e sp ectrum analyzer. th e spectrum analy zer provides the ref in for the synthesizer; offset frequency = 1 khz. 11 f refin = 10 mhz; f pfd = 200 khz; n = 2500; loop b/w = 10 khz. 12 f refin = 10 mhz; f pfd = 1 mhz; n = 500; loop b/w = 25 khz. 13 the spurious signals are meas ured with the eval-adf4360- xeb1 evaluation board and the hp 8562e spectrum analyzer. the spectrum analyzer provides the ref in for the synthesizer; f refout = 10 mhz @ 0 dbm.
adf4360-7 r e v. a | pa ge 5 o f 2 8 timing characteristics 1 av dd = d v dd = v vc o = 3.3 v 10%; a g nd = d g nd = 0 v ; 1. 8 v a nd 3 v log i c lev e l s us ed; t a = t min to t max , u n l e s s o t h e r w i s e n o t e d . table 2. parameter limit at t min to t ma x (b version ) unit test condition s /comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le set u p time t 7 20 ns min le pulse width 1 re fe r to the s e ctio n fo r the re co mmende d p o wer-up proce d ur e for this device. po we r - u p cloc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04441-002 f i g u re 2. ti ming d i ag r a m
adf4360-7 r e v. a | pa ge 6 o f 2 8 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v vco to gnd ?0.3 v to +3.9 v v vco to av dd ?0.3 v to +0.3 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in to gnd ?0.3 v to v dd + 0.3 v operating tem p erature range maximum junction temperature 150c csp ja thermal impedance paddle soldered 50c/w paddle not soldered 88c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t - i n g on ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e m a xi- m u m r a t i n g condi t i on s fo r ex ten d e d p e r i o d s m a y a f fe c t de vice rel i a b i l it y . this de vice is a hig h p e r f o r ma n c e rf in t e g r a t e d cir c ui t wi t h an e s d r a t i ng of < 1 k v , a n d it i s e s d s e ns it ive. pr op e r pre c aut i on s s h o u ld b e ta k e n f o r ha n d lin g and as s e m b l y . transis t o r count 12543 (cm o s) a nd 700 (b i p ol ar) esd caution esd (electrostatic discharge) sensitive device. ele c tr ostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharg e wit h out detection. althou gh this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adf4360-7 r e v. a | pa ge 7 o f 2 8 pin conf iguration and fu nction descriptions adf4360-7 top view (not to scale) cpgnd 1 av dd 2 agnd 3 rf out a 4 rf out b 5 v vco 6 data 18 clk 17 ref in 16 dgnd 15 c n 14 r set 13 v tune 7 agnd 8 l1 9 l2 10 agnd 11 c c 12 cp 24 ce 23 agnd 22 dv dd 21 mux o u t 20 le 19 04441-003 pin 1 identifier f i gure 3. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 cp gnd charge p u mp ground. t h is is the ground return path for the c h arge pump. 2 a v dd anal og p o w e r supply. t h is ranges from 3.0 v to 3.6 v. decoup ling capacitors to the a n alog ground p l a n e should be placed as close a s possible to this pin. av dd must have the same value as dv dd . 3, 8, 11, 22 agnd analog grou nd. this is the gr ound return path of the presc a l e r and vco. 4 r f ou t a vco output. the output l e ve l is pr ogrammabl e fro m ?5 dbm to ?1 4 dbm. see the o u tput matchi ng section for a description of the various output stages. 5 r f ou t b vco compl e mentary output. t h e output l e vel is pr ogramma ble fro m ?5 dbm to ?1 4 dbm. see the o u tput matchi ng section for a description of the various output stages. 6 v vco po wer supp ly for the vco. this ranges from 3.0 v to 3.6 v. d e coupl i ng c a pac i tors to the anal og ground pl ane shoul d be pla c ed as clos e as possible to t h is pin. v vco must have the same value as av dd . 7 v tu n e control i n put to t h e vco. this vo lt age determines the ou tput freque ncy and is derive d from filtering t h e cp out p ut vol t age. 9 l1 an externa l indu ctor to a g nd should be connect e d to this pin t o set the a d f43 60-7 output frequen c y. l1 and l 2 need to be t h e same value. for inductances greater than 3. 3 nh, a 470 ? resistor should be added in pa rallel to agn d . 10 l2 an externa l indu ctor to a g nd should be connect e d to this pin t o set the a d f43 60-7 output frequen c y. l1 and l 2 need to be t h e same value. for inductances greater than 3. 3 nh, a 470 ? resistor should be added in pa rallel to agn d . 1 2 c c internal compensation node. t h is pin must be decoupled t o groun d with a 10 nf ca pacitor. 1 3 r set connecting a resistor between thi s pin and cpgnd se ts the maximum charge pump output current fo r the synthesizer. t h e nominal vo ltage potential at t h e r set pin is 0.6 v. the relationship be twe en i cp and r se t is set cpmax r i = where r set = 4.7 k ? , and i cpmax = 2.5 ma. 1 4 c n internal compensation node. t h is pin must be dec o upled t o v vc o with a 10 f capaci tor. 15 dgn d dig i ta l gr ound. 1 6 r e f in reference input. this is a cmos input wit h a nominal thresho l d of v dd / 2 and a dc equi val e nt input resis tanc e of 100 k? (see figure 16). this input can be driven from a ttl or cmos crystal osci llator, or it can be ac -c oupled. 17 clk serial cl ock input. t h is serial c l ock is used to c l oc k i n the serial data to the registers. the data is latche d into th e 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 18 d a t a serial d a ta input. t h e serial data is l o aded msb firs t with t h e two lsb s being the contr o l bits. this input is a high impedance cmos input. 19 le load enable, cmos inpu t. when l e goes high, the data stored in the shift registers is loaded into o n e of the four la tches, a n d t h e r e lev a nt la t c h is s e lected u sing t h e contr o l bits. 20 muxou t this m u ltip lexer ou tpu t a l lo ws either the lo ck dete ct , the sca l ed rf, or the scaled referenc e frequenc y to be acc e ss ed externall y . 2 1 d v dd d i gital p o w e r su pply. t h is ranges from 3.0 v to 3.6 v. decoup ling capacitors to the di gital ground plan e should be placed as close a s possible to this pin. dv dd must h a ve the same value as av dd . 23 c e c h ip ena b le. a l o g i c lo w on t h is pi n po wer s dow n t h e devic e and pu ts the c h arge pu mp into three- state mode. taking the pin hi gh po wers up th e device depe ndi n g on the status of the po wer-do wn bits. 2 4 c p ch arge p u mp o u tp u t . wh en e n abl e d , th i s p r o v id e s i cp to t h e e x ter n a l loo p fi lter, whi c h i n t u rn dri v es t h e i n t e rna l vc o.
adf4360-7 r e v. a | pa ge 8 o f 2 8 typical perf orm ance cha r acte ristics ?150 ?120 ?130 ?140 ?7 0 ?6 0 ?9 0 ?100 ?110 ?8 0 ?4 0 ?5 0 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04441-004 f i gure 4. o p en-l o o p vc o p h ase n o ise , l1, l 2 = 1 3 n h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04441-005 f i g u re 5. v c o p h as e n o is e , 50 0 m h z, 2 00 k h z pfd , 10 k h z l oop b a ndw i dt h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04441-006 f i g u re 6. v c o p h as e n o is e , 25 0 m h z, d i v i d e -by-2 e n ab le d 20 0 k h z pfd , 10 k h z l o op b a ndw i dt h 04441-007 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ? 1khz 500mhz 1khz 2khz ?96.4dbc/hz reference level = ? 3.5dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9 seconds averages = 10 f i g u re 7. cl os e - in phas e n o is e at 5 0 0 m h z ( 2 0 0 k h z ch a nnel spa c ing ) 04441-008 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 0.25mhz ? 0.1mhz 1250mhz 0.1mhz 0.25mhz ? 74dbc reference level = ? 3dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 1khz video bandwidth = 1khz averages = 20 f i g u re 8. r e f e r e n c e spurs at 50 0 m h z (200 kh z ch anne l s p ac ing , 10 khz l o op bandw i dth) 04441-009 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 1.1mhz ?0.55mhz 500mhz 0.55mhz 1.1mhz ? 79dbc reference level = ? 3dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 25khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 4.2 seconds averages = 20 f i g u re 9. r e f e r e n c e spurs at 50 0 m h z (1 mh z ch anne l sp ac ing , 25 khz l oop bandw i dth)
adf4360-7 r e v. a | pa ge 9 o f 2 8 ?150 ?120 ?130 ?140 ?7 0 ?6 0 ?9 0 ?100 ?110 ?8 0 ?4 0 ?5 0 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04441-010 f i g u re 10. o p en-l o o p v c o p h as e n o is e , l 1 and l 2 = 1. 0 n h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04441-011 f i gure 11. vc o pha s e no ise , 1 2 5 0 m h z , 2 00 k h z pfd , 10 k h z l o op b a ndw i dt h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04441-012 f i gur e 1 2 . vc o p h ase noi s e , 62 5 mh z , d i v i d e -by-2 e n ab le d 20 0 k h z pfd , 10 k h z l o op b a ndw i dt h 04441-013 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ? 1khz 1.25ghz 1khz 2khz ? 87.5dbc/hz reference level = ? 3.5dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9 seconds averages = 20 f i g u re 13. cl os e - in p h as e n o is e at 1 2 5 0 m h z (2 0 0 k h z ch anne l sp ac ing ) 04441-014 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 0.25mhz ? 0.1mhz 1250mhz 0.1mhz 0.25mh z ? 79dbc reference level = ? 3dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 1khz video bandwidth = 1khz averages = 20 f i gur e 1 4 . re fe r e nc e spur s a t 125 0 mh z (200 kh z ch anne l s p ac ing , 10 khz l o op bandw i dth) 04441-015 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 1.1mhz ?0.55mhz 1250mhz 0.55mhz 1.1mhz ? 79dbc reference level = ? 3dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 25khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 4.2 seconds averages = 20 f i gur e 1 5 . re fe r e nc e spur s a t 125 0 mh z (1 mh z ch anne l sp ac ing , 25 khz l oop bandw i dth)
adf4360-7 rev. a | page 10 of 28 circuit description reference input section t h e re f e re nc e i n put st ag e i s s h ow n i n f i g u re 1 6 . s w 1 a n d s w 2 a r e n o r m al ly clos e d s w i t ch es. sw3 is n o r m al ly o p en. w h e n p o w e r - do w n is i n i t ia te d , sw3 is clo s e d , a nd s w 1 a nd sw2 a r e o p ene d . this ens u r e s t h a t t h er e is n o lo adin g o f t h e ref in pi n on p o we r - d o w n . 04441-016 buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control f i gure 16. r e ference input stag e prescaler (p/p + 1) the d u al- m o d u l us p r es caler (p/p + 1), alo n g wi t h t h e a and b co un t e rs, ena b les th e l a rg e divisio n ra tio , n, t o b e r e alize d (n = b p + a). th e d u al -m o d u l us p r es caler , o p era t in g a t cml lev e ls , ta k e s th e c l oc k f r o m th e v c o a n d d i v i de s i t d o wn t o a ma na ge ab le f r e q uen c y fo r t h e cmos a and b co un ters. t h e p r es caler is p r og ra mma b l e . i t c a n be s e t in s o f t wa r e t o 8/9 o r 16/17 an d is b a s e d o n a sy n c hr on o u s 4/5 co r e . a val u e o f 32/33 ca n be p r og ra mm e d b u t i t is n o t us ef u l o n this p a r t . th er e is a minim u m divide ra tio p o s s ib le f o r f u l l y co n t igu o us o u t p u t f r eq uen c ies; this minim u m is det e r m in ed b y p , th e p r es caler va l u e, a nd is g i ven b y (p 2 ? p). a and b counters the a an d b c m os co un t e rs c o m b i n e w i t h t h e d u a l - m o d u l us p r escaler t o allo w a wid e ran g e d i visio n ra t i o in th e pll f e e d - bac k co u n t e r . th e co u n t e rs a r e s p ecif ie d t o w o rk w h en the p r es caler o u t p u t is 300 mh z o r les s . th us, wi th a v c o f r eq uen c y o f 2.5 gh z, a p r es caler val u e o f 16/17 is valid , b u t a val u e o f 8/9 is no t valid . a t f u nda m e n t a l v c o f r e q uen c ie s les s tha n 700 mh z, a val u e o f 8/9 is best. pulse swallow function the a an d b coun t e rs, in con j u n c t ion wi t h the d u al -m o d u l us p r es caler , mak e i t p o s s ib le t o g e n e ra t e o u t p u t f r eq uen c ies tha t a r e s p a c ed o n l y b y th e r e f e r e n c e f r eq ue n c y d i v i d e d b y r . th e v c o f r eq uen c y eq ua ti o n i s () / ] [ + = w h er e: f vc o is th e o u t p u t f r eq uen c y o f th e v c o . p is t h e p r es et m o d u l u s o f t h e d u al - m o d u l us p r es caler (8/9 o r 16/17). b is th e p r es et di vide ra ti o o f th e b i na r y 1 3 -b i t co un t e r (3 t o 81 91 ) . a is t h e p r es et div i de r a t i o o f t h e b i na r y 5 - b i t s w a l lo w co u n t e r (0 t o 3 1 ). f refin is t h e ext e r n al r e fer e n c e f r e q uen c y os ci l l a t or . n = bp + a to pfd from vco n divider modulus control load load 13-bit b counter 5-bit a counter prescaler p/p+1 04441-017 f i gure 17. a and b counters r counter t h e 14-b i t r co un t e r all o w s th e i n p u t r e f e r e n c e f r eq ue n c y t o b e divide d do w n t o p r o d uce t h e r e fer e n c e clo c k t o t h e phas e f r eq uen c y det e c t o r (p fd). di vis i o n ra tios f r o m 1 t o 16,383 a r e al lo w e d . pf d an d c h arge pump the p f d t a k e s i n p u ts f r o m t h e r co un t e r and n co un t e r ( n = bp + a ) an d pro d u c e s a n o u tput prop or t i on a l to t h e ph a s e a n d f r eq ue n c y d i f f e r e n ce bet w ee n t h em . f i g u r e 18 i s a s i m p l i - f i e d s c h e ma t i c. the p f d i n cl u d es a p r og ra mma b l e dela y e l e - m e n t tha t co n t r o ls th e wi d t h o f th e a n t i ba ckla s h p u lse . t h i s p u ls e en s u r e s t h a t t h er e is n o de ad zon e i n t h e pfd t r a n sfer f u n c t i on an d m i nim i zes phas e n o is e an d r e fer e n c e sp urs. t w o b i ts in t h e r coun t e r l a t c h, abp2 a n d abp1, c o n t r o l t h e wi d t h o f t h e p u ls e (s e e t a b l e 9). 04441- 018 programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider c p outpu t r divider n divider cp cpgnd v p f i gur e 1 8 . p f d simpl i f ie d s c hema ti c and t i mi ng (in l o c k )
adf4360-7 rev. a | page 11 of 28 muxout a n d loc k de tect the o u t p u t m u l t i p lexer o n th e ad f4360 fa mily al lo ws th e us er t o acces s v a r i o u s in t e r n al p o in ts o n t h e chi p . th e st a t e o f mux o ut is con t r o l l ed b y m3, m2, a n d m1 in t h e f u n c tion la t c h. th e f u l l tr u t h ta b l e is sh o w n in t a b l e 7. f i gur e 19 s h o w s th e mux o ut s e cti o n in b l oc k d i a g ra m f o rm . lock det e ct mux o ut can be p r og ra mm e d f o r tw o typ e s of lo c k det e c t : dig i t a l an d analog. dig i tal lo ck det e c t is ac t i v e hig h . w h e n ldp in t h e r co u n t e r la t c h is s e t t o 0, dig i tal lo ck detec t is s e t hig h w h en t h e phas e er r o r o n t h r e e co n s e c u t i v e phas e det e c t o r c y cles is les s tha n 15 ns. w i t h ld p s e t t o 1, f i v e co n s ec u t i v e c y c l es o f les s tha n 15 n s phas e er r o r a r e r e q u ir e d t o s e t t h e lo ck dete c t . i t s t a y s s e t hig h un til a p h as e er r o r o f g r ea t e r tha n 25 n s is det e c t ed o n an y subs e q u e n t pd c y cl e. the n-c h a n ne l o p en-dra in a n al og lo c k det e c t sh o u ld be o p era t e d wi t h an ext e r n al p u l l -u p r e sis t o r o f 10 k? n o minal . w h en a lo c k has been det e c t e d , this o u t p u t is hig h wi th na r r o w lo w-g o in g p u ls es. r counter output n counter output digital lock detect dgnd control mux muxout dv dd analog lock detect sdout 04441-019 f i g u re 19. m u x o u t ci r c u i t inpu t shift register the ad f4360 f a mil y s dig i tal s e c t io n in c l udes a 24-b i t in p u t s h if t r e g i st er , a 14-b i t r co u n t e r , a n d an 18-b i t n co un t e r co m p r i s e d o f a 5-b i t a co un ter a n d a 13 -b i t b c o un t e r . da t a is c l o c k e d in t o the 24-b i t s h if t r e g i s t er o n each r i sin g edg e o f cl k. the da t a is c l o c k e d in ms b f i rst. da t a is tra n sf er r e d f r o m th e s h if t r e g i st er t o o n e o f f o ur la t c h e s on the r i sin g edg e o f le. th e dest in a t io n la t c h is det e r m i n e d b y t h e st a t e o f t h e tw o co n t r o l b i ts (c2, c1) in t h e shif t r e g i st er . th es e a r e t h e t w o ls bs, d b 1 a n d d b 0, sh o w n in f i gur e 2. the t r u t h t a b l e fo r t h es e b i ts is s h own i n t a b l e 5. t a b l e 6 s h o w s a s u mma r y o f ho w t h e l a t c h e s ar e p r og ra mm e d . n o t e t h a t t h e te st mo d e l a tch i s u s e d for f a c t or y te st i n g and s h ou l d not b e p r og ra mm e d b y t h e us er . table 5. c2 an d c1 truth ta ble control bits c2 c1 data latch 0 0 control latch 0 1 r counter 1 0 n counter (a an d b) 1 1 test mode latc h vco the v c o co r e in the ad f4360 fa mil y us es eig h t o v erla p p i n g ba nds, as sh o w n in f i gur e 20, t o al lo w a wide f r eq uen c y ra n g e t o b e c o v e re d w i t h out a l a r g e v c o s e n s it i v it y ( k v ) a n d r e s u l t an t p o o r phas e n o is e a n d s p ur io us p e r f o r ma n c e . t h e co rr ect ba n d i s c h osen a u t o m a ti call y b y th e ba n d s e l e ct log i c a t p o w e r - u p o r wh enev er t h e n co un t e r l a tc h is u p da t e d . i t i s i m po r t a n t tha t th e co rr ect w r i t e seq u en ce b e f o ll o w ed a t p o w e r - u p . this s e q u e n ce is: 1. r c o u n te r l a tc h 2. c o n t r o l la t c h 3. n c o u n te r l a tch d u r i n g b a n d s e l e c t , w h i c h t a k e s f i v e p f d c y c l e s , t h e v c o v tun e i s d i s c on ne c t e d f r om t h e output of t h e l o op f i lte r and c o n n e c t e d to an i n te r n a l re fe re nc e volt age. 0.5 1.5 1.0 2.5 2.0 3.0 450 500 550 600 650 frequency (mhz) voltage (v) 04441-020 fi g u r e 2 0 . fr e q u e n c y v s . v tu ne , a d f4 3 60- 7 th e r co un t e r o u t p u t is us e d as th e clo c k fo r t h e b a n d s e le c t log i c a n d s h o u ld n o t e x ce e d 1 m h z. a p r ogra mm a b le di vide r i s p r o v ided a t th e r co un t e r in p u t t o al l o w di vi sio n b y 1, 2 , 4 , o r 8 a n d is co n t r o lle d b y bi ts bsc1 a n d bsc2 in t h e r co un t e r la t c h. w h er e th e r e q u i r ed p f d fr eq u e n c y e x c eed s 1 mh z , th e d i v i d e ra ti o s h o u l d be s e t t o all o w e n o u g h tim e f o r c o rr ec t ba n d s e lectio n.
adf4360-7 rev. a | page 12 of 28 i f t h e o u t p u t s a r e us e d i n divid u al l y , t h e o p t i m u m o u t p u t st a g e co n s is ts o f a sh un t i n d u c t o r t o v dd . af t e r ba nd s e lec t io n, n o r m al pl l ac tio n r e s u m e s. th e val u e o f k v is det e r m in ed b y t h e val u e o f ind u c t o r s us ed (see th e c h oos i n g th e c o rr ect i n d u cta n ce s e ctio n ) . i f d i vi d e -b y- 2 o p era t ion has been s e lec t e d (b y p r og ra mmin g d i v2 [d b22] hig h in t h e n coun t e r l a t c h), th e val u e is hal v ed . the ad f4360 fa mi ly co n t a i n s lin e a r i z a t io n circ ui t r y to minim i z e an y va r i a t ion of t h e pro d u c t o f i cp an d k v . an o t h e r f e a t ur e o f th e ad f436 0 fa mil y i s tha t th e s u p p l y c u rr en t t o t h e r f o u t p u t s t a g e is s h u t d o w n un t i l t h e p a r t a c hie v es lock as m e as ur ed b y th e dig i tal lo c k d e t e ct ci r c ui tr y . this i s ena b led b y th e m u t e -til l- lo c k de t e c t (mtld) b i t in th e co n t r o l la t c h. vco rf out ar f out b buf f e r/ di v i de by 2 04441-021 the o p er a t in g c u r r en t in t h e v c o co r e is p r og ra mma b l e i n fo ur s t eps: 5 ma, 10 ma, 15 ma, and 20 ma. this is co n t r o l l ed b y b i ts pc1 and p c 2 in t h e con t rol la t c h. outpu t st age the rf ou t a and rf ou t b p i n s of th e ad f4360 f a mil y a r e co n- n e c t e d t o t h e col l e c t o rs o f a n np n dif f er en t i al p a ir dr i v en b y b u f f er ed o u t p u t s o f th e v c o , as s h o w n in f i gure 21. t o al lo w t h e us er t o o p t i mi ze t h e p o w e r dis s i p a t io n vs. t h e o u t p ut p o w e r r e q u ir em e n ts, t h e t a i l c u r r en t of t h e dif f er en t i al p a ir is p r o- g r a mma b l e via b i ts p l 1 and p l 2 in t h e con t r o l la t c h. f o ur c u r - r e n t leve ls ma y be s e t: 3.5 ma, 5 ma, 7.5 ma, and 11 ma. th es e lev e l s g i v e o u t p u t p o w e r lev e l s o f ?14 db m, ?11 db m, ?8 dbm, a n d ?5 dbm, r e s p ec ti ve l y , usin g a 50 ? r e sis t o r t o v dd an d a c co u p lin g in t o a 50 ? lo ad . al t e r n a t i v e l y , bo t h ou t p u t s can be co m b in e d in a 1 + 1:1 tra n sf o r m e r o r a 180 mic r os tr i p co u p ler ( s e e t h e o u tput m a tchi ng s e c t i o n) . f i g u re 21. o u t p ut s t ag e a d f4 3 60- 7
adf4360-7 rev. a | page 13 of 28 latch structure t a b l e 6 sh o w s th e thr e e on-chi p la t c h e s f o r the ad f4360 fa mily . th e tw o ls bs decide which la t c h is p r og ra mm e d . table 6. latch structure db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr m1 m2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 co nt r o l bi ts mu x o u t co ntr o l c urr e n t s e tti ng 2 cu rr e n t set t i n g 1 pr e s c a l e r va l u e core power level output power level db21 db22 db23 po wer- do w n 2 po wer- do w n 1 co unter reset m u te- t i ll- ld c p ga in cp three- state phase det e ct or pol arit y pd2 p1 p2 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 co nt r o l bi ts ban d sel e c t cl o c k an ti - ba ckla s h pu l s e wi d t h 14-bit reference counter db21 db22 db23 lo c k det e ct precision test mo d e bit reserved reserved di vi de- by- 2 di vi de- b y- 2 select bsc2 rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv co nt r o l bi ts 5-bit a counter 13-bit b counter control latch n counter latch r counter latch db21 db22 db23 c p ga in reserved cpg div2 divsel 04441-022
adf4360-7 rev. a | page 14 of 28 table 7. co ntrol latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr m1 m2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 co ntro l bi ts mu x o ut c o nt ro l c urre nt s e tti ng 2 curr e n t s e tti ng 1 p r esc a l er va l u e core power level output power level db21 db22 db23 power- down 2 power- down 1 count er reset mu te - t i ll- ld cp gain cp three- state phase det e ct o r po l arit y pd2 p1 p2 cr 0 1 counter operation normal r, a, b counters held in reset pc2 0 0 10 c o r e po w e r l evel 5m a 10m a 15m a pc1 0 1 11 20m a cp 0 1 charge pump output normal three-state pdp 0 1 phase detector polarity ne g a t i v e po s i t i ve cpg 0 1 cp gain cur re nt s e t t i ng 1 cur re nt s e t t i ng 2 mtld 0 1 mute-till-lock detect di s abl e d e nabl e d m3 m2 m1 ou tp u t three-state output 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect ser i a l d a t a o u t pu t dgnd p2 p1 prescaler value 0 0 8/9 0 1 16/17 1 0 32/33 1 1 32/33 ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 1 0 1 asynchronous power-down 1 1 1 synchronous power-down cpi6 cpi5 cpi4 i cp (ma) cpi3 cpi2 cpi1 4.7k ? 0.31 0.62 0.93 1.25 1.56 1.87 2.18 2.50 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 pl2 pl1 output power level current power into 50 ? (using 50 ? to v vco ) ?14dbm ?11dbm ?8dbm ?5dbm 0 0 1 1 0 1 0 1 3.5ma 5.0ma 7.5ma 11.0ma 04441-023
adf4360-7 rev. a | page 15 of 28 tab l e 8. n cou n ter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv co ntro l bi t s 5-bit a counter 13-bit b counter db21 db22 db23 cp gain divide-by- 2 select divide- by-2 reserved cpg div2 divsel this bit is not used by the device and is a don't care bit. a5 a4 .......... a2 a1 a counter divide ratio 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 2 8 1 1 .......... 0 1 2 9 1 1 .......... 1 0 3 0 1 1 .......... 1 1 3 1 f4 (function latch) fastlock enable cp gain operation charge pump current setting 1 is permanently used 0 0 charge pump current setting 2 is permanently used 1 0 n = bp + a; p is prescaler value set in the control latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ? p). b13 b12 b11 b3 b2 b1 b counter divide ratio .......... 0 00 0 00 0 00 0 00 0 0 0 not allowed .......... 0 0 1 not allowed .......... 0 1 0 not allowed .......... 1 1 1 3 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 8188 .......... 1 0 1 8189 .......... 1 1 0 8190 .......... 1 1 1 8191 04441-024 div2 0 1 divide-by-2 f unda m e nt al o u t p ut divide-by-2 divsel 0 1 divide-by-2 select (prescaler input) f u nd a m ent a l o u t pu t s el ect e d divide-by-2 s e l e c t e d
adf4360-7 rev. a | page 16 of 28 tab l e 9. r cou n ter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 co ntr o l bi ts ba nd sel e c t clo c k an ti - ba ckl as h pu l s e wi dt h 14-bit reference counter db21 db22 db23 lo ck detect precision test mode bit reserved reserved bsc2 rsv rsv test mode bit should be set to 0 for normal operation. r14 r13 r12 r3 r2 r1 divide ratio .......... 0 00 0 00 0 00 0 00 0 01 1 .......... 0 1 0 2 .......... 0 1 1 3 .......... 1 0 0 4 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 16380 .......... 1 0 1 16381 .......... 1 1 0 16382 .......... 1 1 1 16383 these bits are not used by the device and are don't care bits. 04441- 025 ldp lock detect precision 0 three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. abp2 abp1 antibacklash pulse width 0 0 3.0ns 0 1 1.3ns 1 0 6.0ns 1 1 3.0ns bsc2 bsc1 band select clock divider 00 1 01 2 10 4 11 8
adf4360-7 rev. a | page 17 of 28 power-up power-up s e q u en ce the co r r ec t p r og ra mmin g s e q u en c e f o r th e adf4360-7 a f t e r po w e r - u p i s : 1. r c o u n te r l a tc h 2. c o n t r o l la t c h 3. n c o u n te r l a tch initial power-up i n i t ial p o w e r - u p r e f e rs t o p r ogra mmin g the p a r t a f t e r the ap p l i c at i o n o f v o l t a g e t o t h e a v dd , d v dd , v vc o an d c e pi n s . o n ini t ia l p o w e r - u p , a n in t e r v a l is r e q u ir e d b e tw e e n p r og ra mmin g th e con t r o l la t c h an d p r og ra mmin g t h e n co u n t e r l a t c h. this i n t e r v al i s n e ces s a r y t o all o w th e tra n s i e n t b e ha v i o r o f th e ad f4360-7 d u r i n g ini t ial p o w e r - u p t o s e t t le . dur i n g ini t ial p o w e r - u p , a wr i t e t o th e con t r o l l a t c h p o w e rs u p t h e p a r t , an d t h e b i as c u r r en ts o f t h e v c o b e g i n t o s e t t le . i f t h es e c u r r en ts ha v e n o t s e t t le d to wi t h in 10 % o f t h eir st e a d y - s t a t e val u e , and if t h e n co un ter la t c h is t h en p r og ra mm e d , t h e v c o ma y n o t o s ci l l a t e a t t h e de sir e d f r e q uen c y , w h ich do es n o t al lo w th e band s e le c t log i c t o c h o o s e t h e co r r e c t f r e q uen c y ba nd , and the ad f4360-7 ma y n o t achie v e lo c k . i f th e r e co m- m e n d e d i n ter v a l is in s e r t e d , and t h e n co u n t e r la t c h is p r o- g r a m m e d , t h e b a nd s e lec t log i c ca n ch o o s e t h e co r r ec t f r e- q u en c y b a nd , and t h e p a r t lo cks t o t h e co r r e c t f r e q uen c y . t h e d u ra ti o n o f th i s i n t e r v al i s a f f e ct ed b y th e v a l u e o f th e ca p a c i t o r o n t h e c n p i n (p in 14) . this ca p a c i t o r is us ed t o r e d u ce t h e c l os e-in n o is e o f th e ad f4360-7 v c o . th e r e co mme n d e d va l u e o f t h is ca p a ci t o r is 10 f . u s in g t h is va l u e r e q u ir es a n in t e r v al o f 10 m s betw een t h e l a t c hin g in o f th e c o n t rol l a tch b i t s and l a tch i ng i n of t h e n c o u n te r l a tch b i t s . i f a s h o r t e r dela y is r e q u ir ed , the c a p a ci t o r can be r e d u ce d . a s l ig h t phas e n o is e p e n a l t y is i n c u r r e d b y t h is cha n ge , w h ich is f u r t her expla i n e d in t h e t a b l e 10. table 10. c n c a pacitance vs. i n terval a n d phase noise c n va lue recommended interval betwe e n control latch and n counter l a tch open-loop phase noise @ 10 khz offset (l1 and l2 = 1.0 nh) open-loop phase noise @ 10 khz offset (l1 and l2 = 13. 0 nh) 10 f 10 ms ?90 dbc ?99 dbc 440 nf 600 s ?88 dbc ?97 dbc clock power-up data le r counter latch data control latch data n counter latch data required interval control latch write to n counter latch write 04441-026 f i g u re 22. a d f4 36 0-7 p o wer - u p ti mi ng
adf4360-7 rev. a | page 18 of 28 hardware power-up/power-down if the part is powered down via the hardware (using the ce pin) and powered up again without any change to the n counter register during power-down, the part locks at the correct fre- quency, because the part is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <10 ms for 10 f capacitance. the smaller capacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while the part is in power-down, since the part may not lock to the correct frequency on power-up. if it is updated, the correct program- ming sequence for the part after power-up is the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section. software power-up/power-down if the part is powered down via the software (using the control latch) and powered up again without any change to the n counter latch during power-down, the part locks at the correct frequency, because the part is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <10 ms for 10 f capacitance. the smaller capacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while the part is in power-down, because the part may not lock to the correct frequency on power-up. if it is updated, the correct program- ming sequence for the part after power-up is to the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section.
adf4360-7 rev. a | page 19 of 28 control latch with (c2, c1) = (0,0), the control latch is programmed. table 7 shows the input data format for programming the control latch. prescaler value in the adf4360 family, p2 and p1 in the control latch set the prescaler values. power-down db21 (pd2) and db20 (pd1) provide programmable power- down modes. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that pd2 has been loaded with a 0. in the pro- grammed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into bit pd1 (on the condition that a 1 has also been loaded to pd2), the device goes into power-down on the second rising edge of the r counter output, after le goes high. when the ce pin is low, the device is immediately disabled regardless of the state of pd1 or pd2. when a power-down is activated (either synchronous or asynchronous mode), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rf outputs are debiased to a high impedance state. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. charge pump currents cpi3, cpi2, and cpi1 in the adf4360 family determine current setting 1. cpi6, cpi5, and cpi4 determine current setting 2. see the truth table in table 7. output power level bits pl1 and pl2 set the output power level of the vco. see the truth table in table 7. mute-till-lock detect db11 of the control latch in the adf4360 family is the mute- till-lock detect bit. this function, when enabled, ensures that the rf outputs are not switched on until the pll is locked. cp gain db10 of the control latch in the adf4360 family is the charge pump gain bit. when it is programmed to 1, current setting 2 is used. when it is programmed to 0, current setting 1 is used. charge pump three-state this bit puts the charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. phase detector polarity the pdp bit in the adf4360 family sets the phase detector polarity. the positive setting enabled by programming a 1 is used when using the on-chip vco with a passive loop filter or with an active noninverting filter. it can also be set to 0, which is required if an active inverting loop filter is used. muxout control the on-chip multiplexer is controlled by m3, m2, and m1. see the truth table in table 7. counter reset db4 is the counter reset bit for the adf4360 family. when this is 1, the r counter and the a, b counters are reset. for normal operation, this bit should be 0. core power level pc1 and pc2 set the power level in the vco core. the recom- mended setting is 5 ma. see the truth table in table 7.
adf4360-7 rev. a | page 20 of 28 n counter latch table 8 shows the input data format for programming the n counter latch. a counter latch a5 to a1 program the 5-bit a counter. the divide range is 0 (00000) to 31 (11111). reserved bits db7 is a spare bit that is reserved. it should be programmed to 0. b counter latch b13 to b1 program the b counter. the divide range is 3 (00.....0011) to 8191 (11....111). overall divide range the overall divide range is defined by ((p b) + a), where p is the prescaler value. cp gain db21 of the n counter latch in the adf4360 family is the charge pump gain bit. when this is programmed to 1, current setting 2 is used. when programmed to 0, current setting 1 is used. this bit can also be programmed through db10 of the control latch. the bit always reflects the latest value written to it, whether this is through the control latch or the n counter latch. divide-by-2 db22 is the divide-by-2 bit. when set to 1, the output divide-by-2 function is chosen. when it is set to 0, normal operation occurs. divide-by-2 select db23 is the divide-by-2 select bit. when programmed to 1, the divide-by-2 output is selected as the prescaler input. when set to 0, the fundamental is used as the prescaler input. for exam- ple, using the output divide-by-2 feature and a pfd frequency of 200 khz, the user needs a value of n = 5,000 to generate 500 mhz. with the divide-by-2 select bit high, the user may keep n = 2,500. r counter latch with (c2, c1) = (0, 1), the r counter latch is programmed. table 9 shows the input data format for programming the r counter latch. r counter r1 to r14 set the counter divide ratio. the divide range is 1 (00......001) to 16383 (111......111). antibacklash pulse width db16 and db17 set the antibacklash pulse width. lock detect precision db18 is the lock detect precision bit. this bit sets the number of reference cycles with less than 15 ns phase error for entering the locked state. with ldp at 1, five cycles are taken; with ldp at 0, three cycles are taken. test mode bit db19 is the test mode bit (tmb) and should be set to 0. with tmb = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, r counter latch, and n counter latch. note that test modes are for factory testing only and should not be pro- grammed by the user. band select clock these bits set a divider for the band select logic clock input. the output of the r counter is by default the value used to clock the band select logic, but if this value is too high (>1 mhz), a divider can be switched on to divide the r counter output to a smaller value (see table 9). reserved bits db23 to db22 are spare bits that are reserved. they should be programmed to 0.
adf4360-7 rev. a | page 21 of 28 appli c ations frequency generator the wide f r eq u e n c y ra n g e o f the ad4360 -7, p l us th e o n -c hi p divider , ma k e i t a n ideal ch o i ce f o r im p l em en t i ng a n y g e n e ral pu r p o s e c l o c k g e ne r a tor or lo . t o i m ple m en t a clo c k gener a to r in t h e f m b a nd, i t is ne cess a r y t o us e a n ext e r n al divider . th e ad f4007 co n t ain s a ha rd wa r e - p r og ra mma b l e n divider , al lo win g division ra tios o f 8, 16, 32, a n d 64. this divided-do wn sig n al is acces s e d f r o m the mux o ut p i n o f th e ad f4007 . the minim u m f r eq uen c y tha t c a n be f e d t o th e ad f4007 is 500 mh z. th eref o r e , 2.2 nh ind u c t o r s w e r e us ed t o s e t t h e f u ndam en tal f r e q uen c y o f os cil l a t io n a t 1 g h z, wi t h a ran g e f r o m 950 mh z t o 1100 mh z. this a l lo ws f r e q uen c ies as lo w a s 8 mh z and as hig h as 137 mh z t o be g e n e r a t e d usin g a sin g le sys t em. i n t h e cir c ui t dra w n in f i gur e 23, th e ad f436 0-7 is bein g us e d t o g e n e ra t e 1024 mh z, and th e ad f4007 is bein g us ed t o divide b y 8. t o p r o v ide a chan nel sp acin g o f 10 0 khz, a pfd f r e q uen c y o f 800 kh z is us ed f o r th e ad f436 0-7 p ll. th e lo o p ba ndwid t h is c h os en t o b e 20 kh z. the o u t p u t ra ng e o f th e sys t em in f i gur e 23 is a p p r o x ima t e l y 120 mh z t o 135 mh z. the o u t p u t p h as e n o is e is ?104 db c/h z a t 1 kh z o f fs et. u s in g dif f er en t ind u c t o r val u es al lo ws t h e ad f4360-7 t o be us e d t o sy n t h e size an y dif f er en t ra n g e o f f r eq uen c ies o v er th e o p er a t io n o f th e p a r t (235 mh z t o 1800 mh z). adf4007 to lo port vp ref in rf in a m2 m1 cp r set muxout phase frequency detector r counter 2 vdd rf in b n2 n1 04441-027 s p i comp atible s e r ial bus adf4360-7 v vco v vco v vco cpgnd agnd dgnd gnd cpgnd l1 l2 rf out b rf out a fref in cp 1nf 470pf 2.2nh 2.2nh 220pf 6.8nf 51 ? 51 ? 51 ? 4.7k ? 100pf 100pf 1nf 1nf 10 f 4.7k ? 6.2k ? 13k ? r set c c le data clk ref in c n v tune dv dd av dd ce muxout 5 4 24 7 20 23 2 21 6 14 16 17 18 19 13 1 3 8 9 10 11 22 15 12 v dd v dd lock detect charge pump mux n counter 8, 16, 32, 64 fi g u r e 2 3 . fr e q u e n c y g e n e r a t o r
adf4360-7 rev. a | page 22 of 28 choos ing the corre ct inductance value the ad f4360-7 ca n be us e d a t ma n y dif f er en t f r eq uen c ies sim p l y b y c h o o sin g t h e ext e r n al ind u c t o r s t o g i ve t h e co r r e c t o u t p u t f r eq uen c y . f i gur e 24 s h o w s a g r a p h o f b o th minim u m a n d max i m u m f r e q uen c y vs. t h e ex ter n a l ind u c t o r va l u e. the co r r e c t in d u c t or sh o u ld co ver t h e m a x i m u m and min i m u m f r eq uen c ies desir e d . th e ind u c t o r s us ed a r e the 0402 cs typ e f r o m c o ilcra f t. t o r e d u ce m u t u al co u p ling, th e ind u c t o r s sh o u ld be p l ace d a t r i g h t a n g l es t o on e a n o t h e r . a s sh o w n in f i g u r e 24, th e lo w e s t co mm er c i al l y a v a i la b l e va l u e o f in d u c t an ce , 1 . 0 nh, s e ts t h e c e n t er f r eq uen c y a t a p p r o x i- ma te l y 1300 mh z. f o r ind u c t an ces les s than 2. 4 nh, a pcb t r ace sh o u ld b e us e d , a dir e c t sho r t. th e lo w e s t cen t er f r eq uen c y o f oscil l a t ion p o s s i b l e is a p p r o x ima t e l y 350 mh z, w h ich is achi e v e d usin g 30 n h ind u c t o r s. this r e la t i on sh i p ca n b e exp r es s e d b y () ext o l f + = nh 0.9 pf 6.2 2 1 w h er e f o is t h e cen t er f r e q ue n c y , a n d l ex t is t h e ext e r n a l ind u c - ta n c e . 300 500 400 1200 1300 1400 1000 1100 800 900 600 700 1500 0 5 10 15 20 30 25 ext inductance (nh) fre q ue ncy (mhz) 04441-028 f i gure 24. o u tput c e nte r f r equ e nc y vs. ex tern al induc t or v a lu e the a p p r o x ima te val u e o f ca p a c i t a n c e a t t h e mi d p o i n t o f t h e cen t er b a nd o f t h e v c o is 6.2 p f , a n d t h e a p p r o x ima t e val u e o f in t e r n al i n d u c t an ce d u e t o t h e b o nd w i r e s is 0.9 nh. th e v c o se n s i t i v i t y i s a m e as ur e o f th e f r eq ue n c y c h a n g e v s . th e t u n i n g v o l t a g e . i t is a v e r y im p o r t a n t p a ra m eter fo r t h e lo w-p a s s f i l t er . f i g u re 2 5 show s a g r a p h of t h e tu n i ng s e ns it i v it y ( i n m h z / v ) v s . t h e i n d u c t an c e (nh). i t ca n b e s e en t h a t as t h e i n d u c t an ce i n cr ease s , th e sen s i t i v i t y d e cr ea s e s . t h i s r e la ti o n s h i p ca n be d e ri v e d f r o m t h e p r e v i o us eq ua ti o n , i . e . , be ca us e th e in d u cta n ce h a s in cr ea se d , th e c h a n g e in ca pa ci ta n c e f r o m th e v a ra c t o r h a s les s o f a n ef f e c t o n the f r eq uen c y . 0 5 30 25 20 15 10 35 01 0 2 0 30 ext inductance (nh) sen sitivity ( m h z /v) 04441-029 4 0 f i g u re 25. t u n i ng s e ns it iv it y ( i n m h z / v ) v s . induc t anc e ( n h) fixe d freq uency l o f i gur e 26 s h o w s th e ad f4360-7 us ed as a f i xe d f r eq uen c y l o a t 500 mh z. the lo w-p a s s f i l t er was desig n ed usin g ad i s imp l l fo r a cha nnel sp acin g o f 8 mhz a nd an o p e n -lo o p b a ndwi d t h of 30 kh z. th e maxim u m p f d f r eq uen c y o f th e ad f4360-7 is 8 mh z. b e ca us e usin g a la rg er pfd f r eq uen c y al lo ws th e us e o f a sma l ler n, t h e in-b an d ph as e n o is e is r e d u ce d to as lo w as p o s s i b le , ?109 db c/h z . th e typ i cal r m s p h as e no is e (100 h z t o 100 kh z) o f th e l o in this co nf igura t io n is 0.3. t h e r e f e r e n c e fr e q u e n c y i s fr o m a 1 6 m h z t c x o fr o m f o x ; th u s , a n r v a l u e o f 2 i s p r o g ra m m ed . t a k i n g i n t o a c c o un t th e h i gh p f d fr e q ue n c y a n d i t s e f f e ct o n t h e ba n d s e l e ct l o g i c , th e ba n d se l e ct c l oc k div i der is en ab le d . i n t h i s ca s e , a va lue o f 8 is ch o s e n . a ver y s i m - ple p u l l - u p resi st o r and dc b l o c k i ng c a p a ci to r c o m p l e t e t h e r f output s t ag e. s p i com p atible s e r ial bus adf4360-7 v vco v vco fox 801be-160 16mhz v vco cpgnd agnd dgnd l 1 l 2 rf out b rf out a cp 1nf 2.7nf 13nh 470 ? 13nh 470 ? 820pf 27nf 51 ? 51 ? 51 ? 100pf 100pf 1nf 1nf 10 f 4.7k ? 510 ? 910 ? r set c c le data clk ref in c n v tune dv dd av dd ce muxout 5 4 24 7 20 23 2 21 6 14 16 17 18 19 13 1 3 8 9 10 11 22 15 12 v vdd lock detect 04441- 030 fi g u r e 2 6 . fi x e d fr e q u e n c y l o
adf4360-7 rev. a | page 23 of 28 interfacing the ad f4360 f a mil y has a sim p le s p i?-com p a t i b l e s e r i al in t e r - face f o r wr i t in g t o th e de vice . clk, d a t a , and le co n t r o l th e da ta tra n s f e r . w h en l e g o e s h i g h , th e 24 b i t s tha t ha v e been cl o c ke d i n to t h e a ppropr i a t e re g i ste r on e a c h r i s i ng e d g e of c l k a r e t r a n sfer r e d t o t h e a p p r o p r i a te la t c h. s e e f i gu r e 2 fo r t h e ti m i n g di a g ra m a n d t a b l e 5 f o r th e la t c h tr u t h t a b l e . the max i m u m a l lo wa ble s e r i a l clo c k r a te is 20 mh z. t h is m e an s tha t the maxim u m u p da t e ra te p o s s ib le is 833 kh z o r o n e up da t e e v er y 1.2 s. this is cer t a i nly m o r e t h a n ade q u a te fo r sys t em s t h a t ha v e typ i cal lo ck t i m e s in h u ndr e ds o f micr o- sec o n d s . aduc812 interface f i gur e 27 s h o w s th e in t e r f ace betw een t h e ad f 4360 fa mil y an d th e aduc812 m i cr oc o n v e r t er?. b e ca us e t h e aduc812 is bas e d o n a n 8051 co r e , this in t e r f ace c a n be us ed wi th a n y 8051-b a s e d micr o c o n t r ol ler . the micr oc o n v e r t er is s et u p fo r s p i mas ter m o de wi t h cph a = 0. t o ini t i a t e t h e op era t ion, t h e i / o p o r t dr i v in g le is b r o u g h t lo w . e a c h la t c h o f th e adf4360 fa mil y ne e d s a 2 4 - bit word, w h i c h i s a c c o m p l i s h e d by w r it i n g t h re e 8-b i t b y t e s f r o m t h e micr oc on ver t er t o t h e de v i ce . af t e r t h e t h ir d b y t e has b e en wr i t t e n, t h e le in p u t sh o u ld b e b r o u g h t hig h t o com p lete t h e t r an sfer . 04441-031 aduc812 adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi i/o ports f i g u re 27. a d uc8 1 2 t o a d f4 3 60-x i n t e r f ace i/o p o r t lin e s o n the adu c 812 a r e als o us ed t o co n t r o l p o w e r - do wn ( c e i n p u t ) a nd dete c t lo ck ( m u x ou t c o nf igur e d as lo ck det e c t and p o l l e d b y t h e p o r t in p u t). w h en o p e r a t in g i n t h e des c r i b e d m o de, th e maxim u m scl o ck ra te of th e adu c 812 is 4 mh z. this m e an s t h a t t h e maxim u m ra te a t w h ich t h e ou t - p u t f r eq uen c y c a n be c h an g e d is 166 kh z. adsp-2181 interface f i gur e 28 s h o w s th e in t e r f ace betw een t h e ad f 4360 fa mil y an d th e ads p -21xx dig i t a l sig n al p r o c es s o r . the ad f4360 fa mil y n e e d s a 24- b i t s e r i al w o r d fo r e a ch l a t c h wr i t e . the e a siest wa y t o acco m p lish t h is usin g t h e a d s p -21xx fa mi ly is t o us e t h e a u t o b u f f er e d t r an smi t m o de o f o p era t ion wi t h al t e r n a te f r a m - i n g . t h i s prov i d e s a m e ans f o r t r ans m itt i ng an e n t i re bl o c k of se ri al d a ta be f o r e a n in t e rr u p t i s g e n e ra t e d . 04441-032 adsp-21xx adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi tfs i/o ports f i g u re 28. a d s p -2 1 x x to a d f4 3 60-x i n ter f a c e s et u p t h e w o r d len g t h fo r 8 b i t s a nd us e t h r e e m e m o r y lo ca - t i ons f o r e a ch 2 4 - b it word. t o pro g r a m e a ch 2 4 - bit l a tc h , store t h e 8- b i t b y t e s, ena b le t h e a u t o b u f f er e d mo de , a nd wr i t e t o t h e tra n s m i t r e gis t er o f th e d s p . t h i s la s t o p e r a t i o n i n i t ia t e s t h e a u t o b u f f er t r a n sfer . pcb desig n guidelines for chip sc ale packag e the le ads o n t h e chi p s c ale p a cka g e (c p - 24) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e lead len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e le ad w i d t h. th e le ad sh o u ld b e ce n t er e d on t h e p a d t o en s u r e t h a t t h e s o lder join t s i ze is maximize d . the b o t t o m o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r i n t e d cir c ui t b o a r d sh o u ld b e a t le ast as la rg e as t h is e x p o s e d p a d . o n t h e p r in t e d cir c ui t b o a r d , t h er e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n to e n sur e t h a t sh o r t - in g is a v o i de d . ther mal v i as ma y b e us e d on t h e p r i n t e d cir c ui t b o a r d t h er mal p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u ld be in co r p o r a t e d i n t o th e th e r m a l pa d a t a 1.2 mm pi t c h g r id . th e v i a diamet er s h o u ld b e b etw e e n 0.3 mm a nd 0.33 m m , and t h e v i a b a r r el sh o u ld b e pla t e d wi t h 1 o u nce o f co p p er t o p l ug th e via . the us er s h o u ld co nne c t t h e p r i n t e d cir c ui t t h er mal p a d t o a g nd . this is i n t e r n a l ly co nne c t e d t o a g nd .
adf4360-7 rev. a | page 24 of 28 outpu t ma tchi ng ther e a r e a n u m b er o f wa ys t o ma t c h t h e o u t p u t o f t h e ad f4360-7 f o r o p tim u m o p er a t io n; the m o s t b a sic is t o us e a 5 0 ? re s i stor to v vc o . a dc b y p a s s ca p a c i t o r o f 100 pf is co n- ne c t e d i n s e r i e s , a s s h ow n i n fi g u re 2 9 . b e c a u s e t h e re s i stor i s not f r e q u e nc y d e p e nd e n t , t h i s prov i d e s a go o d b r o a db a n d ma t c h. th e o u t p u t p o w e r in t h i s cir c ui t typ i cal l y g i v e s ?5 dbm o u t p u t p o w e r in to a 50 ? lo ad . 100pf 04441-033 rf out v vco 50 ? 51 ? f i g u re 29. si mpl e a d f43 6 0 -7 o u t p ut s t ag e a bet t er s o l u tio n is t o us e a sh u n t ind u c t o r (ac t in g as an rf cho k e) to v vc o . this g i v e s a b e t ter ma t c h an d , t h er efo r e , m o r e o u t p ut p o w e r . a ddi t i ona l ly , a s e r i es in d u c t o r is adde d a f ter t h e d c b y pa s s ca pa ci t o r t o p r o v i d e a r e so n a n t l c c i r c u i t . t h i s t u n e s t h e o s c i l l a tor output a n d prov i d e s a ppro x i m a t el y 1 0 d b a d d i - t i on a l re j e c t i o n of t h e s e c o n d h a r m on i c . t h e sh u n t i n d u c t or n e e d s t o b e a r e l a ti ve l y hig h va l u e (>40 nh). e x p e r i me n t s h a ve sho w n t h a t t h e c i rc u i t s h ow n i n fi g u re 3 0 p r o v ides a n exc e l l en t ma t c h t o 50 ? o v er a limi t e d o p era t i n g ra n g e o f th e adf4360-7 (850 mh z t o 950 m h z). this g i v e s a p p r o x ima t e l y ?2 dbm o u t p u t p o w e r acr o ss t h e sp e c if ic f r eq uen c y ra n g e o f th e ad f436 0-7 usin g 3.9 nh. f o r o t h e r f r e q uen c ies, a tun e d lc is r e commende d . b o t h co m p le m e n t a r y a r c h i t ec t u r e s can b e exa m in e d usin g th e e v al -ad f 4360-7eb 1 ev al ua ti o n boa r d . 7.5nh 47nh 3.9pf 04441-034 rf out v vco 50 ? f i g u re 30. o p t i m u m a d f 4 3 60- 7 o u t p ut st ag e i f t h e us er do es n o t n e e d t h e dif f er en t i al o u t p ut s a v a i la b l e o n t h e ad f436 0-7, t h e us er ma y ei t h er t e r m ina t e t h e un us e d output or c o mbi n e b o t h output s u s i n g a b a lu n . t h e c i rc u i t i n f i g u re 3 1 show s how b e st to c o mbi n e t h e output s . 7.5nh 9.0nh 47nh 9.0nh 3.3pf 100pf 3.3pf 50 ? 7.5nh rf out a v vco rf out b 04441-035 f i g u re 31. ba lun f o r co mb ining a d f4 36 0-7 r f o u t p ut s the cir c ui t in f i gur e 31 is a l u m p ed-l a t t i ce-typ e l c bal u n. i t is desig n e d f o r a cen t er f r eq uenc y o f 900 mh z a nd o u t p u t s 5 . 0 d b m a t this f r eq uen c y . th e s e r i es 7.5 nh in d u c t o r is us ed t o t u n e o u t an y p a rasi t i c c a p a ci t a nce d u e t o t h e b o a r d la yo u t f r o m e a ch i n p u t, and t h e r e mai n der of t h e cir c ui t is u s e d t o shif t t h e o u t p u t o f o n e rf in p u t b y +90 a nd t h e s e cond b y ?90, th us co m b inin g t h e t w o . the ac t i o n o f t h e 9.0 nh i n d u c t o r an d t h e 3.3 pf ca p a ci t o r acco m p lish es t h is. the 47 nh is us ed t o p r o v ide a n rf ch ok e t o f eed the s u p p l y v o l t a g e , and the 100 pf ca p a ci t o r p r o v ides the ne ces s a r y dc b l o c k. t o en s u r e g o o d rf p e r f o r m- a n ce , th e ci r c ui ts i n f i g u r e 30 a n d f i g u r e 31 a r e i m p l em en t e d wi t h c o ilcra f t 0 402/0603 in d u c t o r s a nd a v x 0 402 thin-f il m c a pa ci t o r s . a l ter n a t i v ely , inste a d o f t h e lc b a l u n sh o w n i n f i gur e 31, b o t h o u t p u t s ma y be co m b in e d usin g a 180 ra t-race co u p ler .
adf4360-7 rev. a | page 25 of 28 outline dimensions * compliant to jedec standards mo-220-vggd-2 except for exposed pad dimension 1 24 6 7 13 19 18 12 * 2.45 2.30 sq 2.15 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bo tt om view) f i gure 32. 2 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [ v q_ lfcsp ] 4 mm 4 m m b o d y , v e r y thin q u ad (cp - 24- 2) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge frequency r a ng e package descri ption package option adf4360-7bcp ?40c to +85c 350 mhz to 180 0 mhz 24-lead vq_lf c sp cp-24-2 adf4360-7bcprl ?40c to +85c 350 mhz to 180 0 mhz 24-lead vq_lf c sp cp-24-2 ADF4360-7BCPRL7 ?40c to +85c 350 mhz to 180 0 mhz 24-lead vq_lf c sp cp-24-2 adf4360-7bcpz 1 ?40c to +85c 350 mhz to 180 0 mhz 24-lead vq_lf c sp cp-24-2 adf4360-7bcpzrl 1 ?40c to +85c 350 mhz to 180 0 mhz 24-lead vq_lf c sp cp-24-2 adf4360-7bcpzrl7 1 ?40c to +85c 350 mhz to 180 0 mhz 24-lead vq_lf c sp cp-24-2 eval-adf4360- 7 e b 1 e v a l u a t i o n boar d 1 z = pb-fre e part.
adf4360-7 rev. a | page 26 of 28 notes
adf4360-7 rev. a | page 27 of 28 notes
adf4360-7 rev. a | page 28 of 28 notes purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 a n alo g devic e s, inc. all rig h ts res e rve d . t r ade m arks a n d re g i s - tered trade m arks are the property of their respective owners . d04441C0C 11/04(a)

▲Up To Search▲

Price & Availability of ADF4360-7BCPRL7

	To Download ADF4360-7BCPRL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .